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Authoritative implementation plan for reclassifying gate cadence in dev-cycle and dev-refactor. Target: ~40-50% wall-clock reduction without reducing reviewer count, coverage thresholds, or quality gates. X-Lerian-Ref: 0x1 |
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| .. | ||
| plans | ||
| AGENT_DESIGN.md | ||
| coderabbit-instructions.md | ||
| FRONTMATTER_SCHEMA.md | ||
| PROJECT_RULES.md | ||
| PROMPT_ENGINEERING.md | ||
| WORKFLOWS.md | ||